The current method of circuit design is to create logic circuits and array circuits which operate at a specific power level. There are numerous teachings in the art of circuits used to maintain a specific power level or specific current level within a logic gate. In particular, current switch technology has additional circuitry on the chip to minimize current level changes within the logic gate while temperature, power supplies, and lot to lot processes vary. FIG. 1 shows a typical logic speed power curve with an arrow showing the current design practice--pick a power level, maintain the power level and accept the resulting circuit speed (gate delay). The design problem is trying to minimize the performance changes under a variety of conditions. The gate delay versus power curve in FIG. 1 can move in any direction and even change slope. At the same time, the power regulating circuitry has its own perturbations. These result in a wide distribution of logic gate speeds.
FIG. 2 shows a gate delay versus power curve used to illustrate the preferred design technique. (Reference is made to U.S. patent application Ser. No. 150,762.) The speed or delay of the logic gate is selected and the power within the circuit is adjusted to achieve this speed. This is accomplished by designing on chip circuitry sensitive to the transient performance characteristics of the on chip logic or array circuits. This special circuitry (delay regulator) will generate a signal indicative of the chip performance (speed vs. power characteristic) to be compared to a system wide periodic reference signal or clock. The comparison creates a signal which controls the power in the logic and/or array circuitry on chip thereby controlling the performance. [Namely, the point on gate delay versus power curve which corresponds to a fixed gate delay]. By connecting the reference signal to all of the chips in the system, all of the chips will have the same relative performance, i.e., gate delay or speed. Since this is a continuous comparison between the reference signal and the on chip signal, many variables affecting performance, such as power supply, temperature changes, chip to chip process variations, etc., will be minimized or eliminated.
With reference to U.S. Patent numbers and publications, a number of prior art disclosures and teachings in the field of integrated circuits are identified below.
Reference is made to U.S. Pat. No. RE. 29,619 entitled "Constant-Current Digital-to-Analog Converter" granted Apr. 25, 1978 to J. J. Pastoriza.
Reference is made to U.S. Pat. No. 3,602,799 entitled "Temperature Stable Constant Current Source" granted Aug. 31, 1971 to F. J. Guillen.
Reference is made to U.S. Pat. No. 3,743,850 entitled "Integrated Current Supply Circuit" granted July 3, 1973 to W. F. Davis.
Reference is made to U.S. Pat. No. 3,754,181 entitled "Monolithic Integrable Constant Current Source For Transistors Connected As Current Stabilizing Elements" granted Aug. 21, 1973 to W. Kreitz et al.
Reference is made to U.S. Pat. No. 3,758,791 entitled "Current Switch Circuit" granted Sept. 11, 1973 to K. Taniguchi et al.
Reference is made to U.S. Pat. No. 3,778,646 entitled "Semiconductor Logic Circuit" granted Dec. 11, 1973 to A. Masaki.
Reference is made to U.S. Pat. No. 3,794,861 entitled "Reference Voltage Generator" granted Feb. 26, 1974 to J. R. Bernacchi.
Reference is made to U.S. Pat. No. 3,803,471 entitled "Variable Time Ratio Control Having Power Switch Which Does Not Require Current Equalizing Means" granted Apr. 9, 1974 to R. G. Price et al.
Reference is made to U.S. Pat. No. 3,808,468 entitled "Bootstrap FET Driven With On-Chip Power Supply" granted Apr. 30, 1974 to P. J. Ludlow et al.
Reference is made to U.S. Pat. No. 3,978,473 entitled "Integrated-Circuit Digital to Analog Converter" granted Aug. 31, 1976 to J. J. Pastoriza.
Reference is made to U.S. Pat. No. 4,004,164 entitled "Compensating Current Source" granted Jan. 18, 1977 to H. C. Cranford, Jr., et al.
Reference is made to U.S. Pat. No. 4,029,974 entitled "Apparatus for Generating A Current Varying With Temperature" granted June 14, 1977 to A. P. Brokaw.
Reference is made to U.S. Pat. No. 4,100,431 entitled "Integrated Injection Logic to Linear High Impedance Current Interface" granted July 11, 1978 to J. J. Stipanuk.
Reference is made to U.S. Pat. No. 4,145,621 entitled "Transistor Logic Circuits" granted Mar. 20, 1979 to S. F. Colaco.
Reference is made to U.S. Pat. No. 4,160,934 entitled "Current Control Circuit For Light Emitting Diode" granted July 10, 1979 to H. C. Kirsch.
Reference is made to U.S. Pat. No. 4,172,992 entitled "Constant Current Control Circuit" granted Oct. 30, 1979 to D. D. Culmer et al.
Reference is made to U.S. Pat. No. 3,736,477 entitled "Monolithic Semiconductor Circuit For A Logic Circuit Concept of High Packing Density" granted May 29, 1973 to H. H. Berger et al. The Berger et al. patent discloses basic I.sup.2 L structure and circuitry.
Reference is made to the following IBM technical Disclosure Bulletin Publications:
(1) "Current Source Generator" by G. Keller et al., Vol. 12, No. 11, April 1970, page 2031; PA1 (2) "Precision Integrated Current Source" by A. Cabiedes et al., Vol. 13, No. 6, November 1970, page 1699; PA1 (3) "Voltage Reference Buffer" by J. A. Dorler et al., Vol. 14, No. 7, December 1971, page 2095; PA1 (4) "Adjustable Underfrequency-Overfrequency Limiting Circuit" by W. B. Nunnery, Vol. 15, No. 6, November 1972, pages 1927-9; PA1 (5) "Reference Voltage Generator and OFF-Chip Driver For Current Switch Circuit" by A. Brunin, Vol. 21, No. 1, June 1978, pages 219-20; and PA1 (6) "Gated Current Source" by J. W. Spencer, Jr., Vol. 21, No. 7, December 1978, pages 2719-20. PA1 (1) "Integrated Injection Logic Shaping Up As Strong Bipolar Challenge to MOS", Electronic Design 6, Mar. 15, 1974, pages 28 and 30. PA1 (2) "I.sup.2 L Puts It All Together For 10-bit A-D Converter Chip" by Paul Brokaw, Electronics, Apr. 13, 1978, pages 99-105. PA1 (3) "Delay Regulation A Performance Concept", by E. Berndlmaier, J. A. Dorler, J. M. Mosley and S. D. Weitzel, Proceedings of the IEEE International Conference on Circuits and Computers, ICCC80, Volume 2 of 2, edited by N. B. Guy Rabbat, Oct. 1-3, 1980, Rye Town Hilton Inn, Portchester, New York, IEEE Catalog No. 80CH1511-5, Library of Congress Catalog Card No. 79-90696.
Reference is also made to the following publications: